Teardown 2026

Current State of
Open Silicon

My experience supporting wafer.space's first production run, the projects that shipped on it, and the opportunities that lie ahead.

Andrew Wingate · Evezor Inc. · evezor.com

Introduction

Who am I — Andrew Wingate

Evezor Inc.

President

Open source robotics and automation.

evezor.com

Chipy

Board — Secretary

Chicago Python User Group. Python conferences and networking for the Chicago area.

chipy.org

Pumping Station: One

Area Host — Volunteer

Chicago's largest community-run makerspace.

pumpingstationone.org

Contracting

Silicon design & manufacturing services for wafer.space.

Launched on Crowd Supply

Tobor — the robotic arm.

Background

What is Silicon?

Silicon refers to integrated circuits (ICs) — the physical substrate where transistors and wires are combined to create logic blocks.

It's used to create many of the larger components you already know:

CPU GPU Memory Radios Amplifiers

Closeup of dies on a wafer — Dies on a finished wafer

Prior Art — PCBs

What OSH Park Did

PCB ordering used to be painful. OSH Park fixed it with an online tool where you upload your design — drag & drop a file and:

Instant quote
Instantly verify your design — see a 3D render
Published fab specifications
Pool orders into a single panel
Panels come back, designs get separated and shipped to customers

OSH Park purple PCB panel — Pooled purple panels

Compute — how do you get yours?

A Full Die of Your Own

1wafer.space gets 50 full wafers from the foundry.

2Each wafer has many reticle shots.

3Each reticle has many projects — one of which could be your design.

1000 dies of your design

Wafer map of reticle shots — Reticle shots across the wafer

The Journey Begins

First Stop — Singapore

Logistics

Get the Wafers

Wafer shipment arrives — The shipment arrives

Opening the wafer carrier — Opening the carrier

Wafer carriers — Wafer transport carriers

Wafer in its case — One of 50 production wafers

Logistics

Do the Sort

Wafer on sorting rig — Wafer loaded on the rig

Wafer on machine — Working through the stack

Projects on Run #1

ISHI-KAI

github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1

Projects on Run #1

Tholin

6502 / 6510 / PLA replicas
SID replicas
rv32ima_zicsr_smnmi core
Retro DRAM controller
GPIO chip
NTSC test signal generator
FM synth
Digital-to-analog converters
Various demos

Projects on Run #1

The wafer.space Logo — in Silicon

Logo drawn in metal layers

Die under microscope — Under the microscope

Inspecting the shots

Projects on Run #1

BreakingTTAPs — a Transport-Triggered CPU

A processor with no opcodes — you program it by moving data. Operations fire the moment their operands arrive at a functional unit.

Transport-Triggered Architecture in SystemVerilog
Verified with cocotb, taped out via LibreLane
On the wafer.space GF180MCU first shuttle

Created by

Breaking Taps

youtube.com/@BreakingTaps

GitHubgithub.com/polyfractal/BreakingTTAPs

BreakingTTAPs GDS render — The GDS, rendered — the Breaking Taps logo is in the die art

Projects on Run #1

FABulous eFPGA

48× I/Os
480× LUT4 + FF, with carry chain
60× MUX — 1×MUX8, 2×MUX4 or 4×MUX2
6× SRAM 512×8, individual bit-enable
6× MAC — 8bit×8bit + 20bit, sign-extend
12× register files — 32×4bit, 1w1r1r
Global clock network
WARMBOOT — reconfigure from one of 16 slots

An open-source FPGA fabric you can reprogram after fab — built with the FABulous framework by mole99.

github.com/mole99/gf180mcu-fabulous-fpga

FABulous eFPGA chip layout — The eFPGA fabric — full chip layout

Projects on Run #1

RZ80 — the Z80, Reborn

The Zilog Z80 turned 50 this month — discontinued 2024
Powered Nintendo's Game Boy, Sega's Master System, Pac-Man, and TI graphing calculators
Open-source, pin-compatible replacement — headed for a drop-in DIP40
Headroom to ~50 MHz vs the original's 4 MHz

github.com/rejunity/
ws0-z80-open-silicon-gf180mcu

RZ80

The Journey Continues

Next Stop — Shenzhen, China

Packaging

CoB — Chip on Board

Chip-on-board package — Bare die bonded into a package

Die closeup in package — The die, wired and ready

Packaging

The Wirebonding House

Operator at wirebonding machine — Operator at the bonder

Wirebonding machine closeup — Bonding head at work

Packaging

Wirebonds, Up Close

Wirebond closeup — Gold ball bonds on the pads

Wirebond closeup at die corner — Die corner, bonded out

Perspective

Node Size & the Performance Gains

Process nodes have shrunk three orders of magnitude since 1971.

Open silicon today lives on mature nodes like GF180 — old by phone standards, but plenty for real, useful chips.

Node size over time: 10um in 1971 to 22nm in 2012 — 10 µm (1971) → 22 nm (2012)

Perspective

What Open Source180 nm Really Gets You

180 nm is Pentium III technology
On the first run, projects were getting 90 nm performance
40% more RAM per given area
Open source opens the door to massive compute on the design side
LibreLane has no per-core licenses

“The industry least served by the advances of silicon has been the silicon industry.”

New Projects — This Run

microTheia — Event-Based Vision

Machine-vision ASIC that classifies motion patterns from an event camera stream
Compresses 320×320 events into a 16×16 grid across 16 temporal windows
Integer MAC scoring against programmable weights — 4 motion classes, reported over SPI
64 MHz core on GF180MCU, clean DRC/LVS, LibreLane + OpenROAD flow

github.com/dhgaddy/microTheia

Event camera data animation — Event stream, live

microTheia chip layout — The chip layout

New Projects — This Run

SlugTPU — a Tensor Processing Unit

Open-source TPU for quantized neural-net inference (8-bit weights & activations)
8×8 INT8 systolic array — 64 MACs/cycle, 32-bit accumulate
2 KiB activation + 2 KiB weight SRAM, custom SDRAM controller for 32 MiB off-chip
Built by UC Santa Cruz students for their capstone course — on a wafer.space 1×1 slot

github.com/SlugTPU/gf180mcu-slugtpu